URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [tags/] [v1p1/] [sim/] [top/] - Rev 29

Rev	Log message	Author	Age	Path
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4488d 10h	/ha1588/tags/v1p1/sim/top/
26	Updated test case.	edn_walter	4490d 11h	/ha1588/tags/v1p1/sim/top/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4491d 12h	/ha1588/tags/v1p1/sim/top/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4492d 06h	/ha1588/tags/v1p1/sim/top/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4492d 10h	/ha1588/tags/v1p1/sim/top/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4493d 06h	/ha1588/tags/v1p1/sim/top/
15	Renamed module name for tsu and rtc. Added folder for reg and top. Added folder for sopc, preparing for Altera SOPC Builder customized component.	edn_walter	4504d 06h	/ha1588/tags/v1p1/sim/top/