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[/] [ha1588/] [trunk/] - Rev 46

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46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4455d 09h /ha1588/trunk/
45 1. optimized area, by removing unused registers.
2. optimized timing, by removing latches.		 edn_walter 4456d 00h /ha1588/trunk/
44 Updated TSU testbench. edn_walter 4456d 02h /ha1588/trunk/
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4457d 00h /ha1588/trunk/
42 Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. edn_walter 4457d 06h /ha1588/trunk/
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4457d 08h /ha1588/trunk/
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4457d 12h /ha1588/trunk/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4458d 09h /ha1588/trunk/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4458d 12h /ha1588/trunk/
36 TSU testbench is now self-checking. Test result is reported at end of simulation. edn_walter 4459d 07h /ha1588/trunk/
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4460d 06h /ha1588/trunk/
34 Added LGPL file header to all copyrighted files. edn_walter 4460d 09h /ha1588/trunk/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4460d 11h /ha1588/trunk/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4460d 13h /ha1588/trunk/
31 Added hand-shaking for the TSU data reading. edn_walter 4461d 06h /ha1588/trunk/
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4461d 06h /ha1588/trunk/
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4461d 06h /ha1588/trunk/
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4461d 13h /ha1588/trunk/
26 Updated test case. edn_walter 4463d 08h /ha1588/trunk/
25 Updated SOPC Builder component and example system. edn_walter 4464d 07h /ha1588/trunk/

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