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[/] [ha1588/] [trunk/] [rtl/] - Rev 39

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Rev	Log message	Author	Age	Path
39	1. Added memory map and feature description. 2. Separated TX RX TSU register addresses.	edn_walter	4459d 10h	/ha1588/trunk/rtl/
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4460d 07h	/ha1588/trunk/rtl/
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4460d 11h	/ha1588/trunk/rtl/
35	Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets.	edn_walter	4462d 05h	/ha1588/trunk/rtl/
34	Added LGPL file header to all copyrighted files.	edn_walter	4462d 07h	/ha1588/trunk/rtl/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4462d 09h	/ha1588/trunk/rtl/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4462d 11h	/ha1588/trunk/rtl/
31	Added hand-shaking for the TSU data reading.	edn_walter	4463d 05h	/ha1588/trunk/rtl/
30	Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit	edn_walter	4463d 05h	/ha1588/trunk/rtl/
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4463d 05h	/ha1588/trunk/rtl/
27	Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s.	edn_walter	4463d 11h	/ha1588/trunk/rtl/
25	Updated SOPC Builder component and example system.	edn_walter	4466d 05h	/ha1588/trunk/rtl/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4466d 06h	/ha1588/trunk/rtl/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4467d 00h	/ha1588/trunk/rtl/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4467d 04h	/ha1588/trunk/rtl/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4468d 01h	/ha1588/trunk/rtl/
20	Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder.	edn_walter	4472d 05h	/ha1588/trunk/rtl/
19	Added pipeline registers to Real Time Clock module to improve timing.	edn_walter	4472d 05h	/ha1588/trunk/rtl/
18	Added QuartusII Place and Route project for top level ha1588.v	edn_walter	4472d 05h	/ha1588/trunk/rtl/
17	Updated reg.v content.	edn_walter	4472d 23h	/ha1588/trunk/rtl/

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[/] [ha1588/] [trunk/] [rtl/] - Rev 39

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