URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [reg/] - Rev 37

Rev	Log message	Author	Age	Path
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4460d 10h	/ha1588/trunk/rtl/reg/
34	Added LGPL file header to all copyrighted files.	edn_walter	4462d 07h	/ha1588/trunk/rtl/reg/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4462d 09h	/ha1588/trunk/rtl/reg/
31	Added hand-shaking for the TSU data reading.	edn_walter	4463d 04h	/ha1588/trunk/rtl/reg/
27	Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s.	edn_walter	4463d 11h	/ha1588/trunk/rtl/reg/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4466d 06h	/ha1588/trunk/rtl/reg/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4467d 00h	/ha1588/trunk/rtl/reg/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4468d 01h	/ha1588/trunk/rtl/reg/
18	Added QuartusII Place and Route project for top level ha1588.v	edn_walter	4472d 05h	/ha1588/trunk/rtl/reg/
17	Updated reg.v content.	edn_walter	4472d 23h	/ha1588/trunk/rtl/reg/
16	Try to add sth.	edn_walter	4476d 16h	/ha1588/trunk/rtl/reg/
15	Renamed module name for tsu and rtc. Added folder for reg and top. Added folder for sopc, preparing for Altera SOPC Builder customized component.	edn_walter	4479d 00h	/ha1588/trunk/rtl/reg/