OpenCores
URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [reg/] - Rev 40

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4455d 04h /ha1588/trunk/rtl/reg/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4456d 01h /ha1588/trunk/rtl/reg/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4456d 05h /ha1588/trunk/rtl/reg/
34 Added LGPL file header to all copyrighted files. edn_walter 4458d 01h /ha1588/trunk/rtl/reg/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4458d 03h /ha1588/trunk/rtl/reg/
31 Added hand-shaking for the TSU data reading. edn_walter 4458d 22h /ha1588/trunk/rtl/reg/
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4459d 05h /ha1588/trunk/rtl/reg/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4462d 00h /ha1588/trunk/rtl/reg/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4462d 18h /ha1588/trunk/rtl/reg/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4463d 19h /ha1588/trunk/rtl/reg/
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4467d 23h /ha1588/trunk/rtl/reg/
17 Updated reg.v content. edn_walter 4468d 17h /ha1588/trunk/rtl/reg/
16 Try to add sth. edn_walter 4472d 10h /ha1588/trunk/rtl/reg/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4474d 18h /ha1588/trunk/rtl/reg/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.