URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [rtc/] - Rev 40

Rev	Log message	Author	Age	Path
39	1. Added memory map and feature description. 2. Separated TX RX TSU register addresses.	edn_walter	4455d 02h	/ha1588/trunk/rtl/rtc/
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4456d 00h	/ha1588/trunk/rtl/rtc/
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4456d 03h	/ha1588/trunk/rtl/rtc/
34	Added LGPL file header to all copyrighted files.	edn_walter	4458d 00h	/ha1588/trunk/rtl/rtc/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4458d 03h	/ha1588/trunk/rtl/rtc/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4462d 21h	/ha1588/trunk/rtl/rtc/
19	Added pipeline registers to Real Time Clock module to improve timing.	edn_walter	4467d 21h	/ha1588/trunk/rtl/rtc/
15	Renamed module name for tsu and rtc. Added folder for reg and top. Added folder for sopc, preparing for Altera SOPC Builder customized component.	edn_walter	4474d 17h	/ha1588/trunk/rtl/rtc/
3	Added function block RTC and its unit test.	ash_riple	4492d 16h	/ha1588/trunk/rtl/rtc/