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[/] [ha1588/] [trunk/] [rtl/] [top/] - Rev 39

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Rev Log message Author Age Path
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4571d 11h /ha1588/trunk/rtl/top/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4572d 08h /ha1588/trunk/rtl/top/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4572d 12h /ha1588/trunk/rtl/top/
34 Added LGPL file header to all copyrighted files. edn_walter 4574d 09h /ha1588/trunk/rtl/top/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4574d 12h /ha1588/trunk/rtl/top/
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4575d 06h /ha1588/trunk/rtl/top/
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4575d 12h /ha1588/trunk/rtl/top/
25 Updated SOPC Builder component and example system. edn_walter 4578d 06h /ha1588/trunk/rtl/top/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4580d 02h /ha1588/trunk/rtl/top/
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 4584d 06h /ha1588/trunk/rtl/top/
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4584d 06h /ha1588/trunk/rtl/top/
17 Updated reg.v content. edn_walter 4585d 00h /ha1588/trunk/rtl/top/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4591d 02h /ha1588/trunk/rtl/top/

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