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[/] [ha1588/] [trunk/] [rtl/] [top/] - Rev 68

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66 Added IP instantiation support for: QSys, XPS and WishBone. ash_riple 4294d 05h /ha1588/trunk/rtl/top/
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4576d 09h /ha1588/trunk/rtl/top/
55 Updated the SOPC Builder example with GMII/MII support. edn_walter 4577d 07h /ha1588/trunk/rtl/top/
54 Added support for MII interface as well as GMII interface. Updated unit and top-level test cases. edn_walter 4577d 07h /ha1588/trunk/rtl/top/
48 1. Added testbench for SOPC Builder example. Need to fully implement the self-check test cases. Just ignore the reported failures, and check the waveform for correct addressing.
2. Added GENERATE BLOCK for top-level addr_in unit selection. In normal top-level instantiation without modify the default addr_is_in_word = 0 parameter, the default address unit is in byte (8bit); When instantiated in SOPC Builder, the address unit is default to word (32bit).		 edn_walter 4584d 05h /ha1588/trunk/rtl/top/
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4588d 23h /ha1588/trunk/rtl/top/
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4589d 06h /ha1588/trunk/rtl/top/
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4589d 10h /ha1588/trunk/rtl/top/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4590d 08h /ha1588/trunk/rtl/top/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4590d 11h /ha1588/trunk/rtl/top/
34 Added LGPL file header to all copyrighted files. edn_walter 4592d 08h /ha1588/trunk/rtl/top/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4592d 11h /ha1588/trunk/rtl/top/
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4593d 05h /ha1588/trunk/rtl/top/
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4593d 11h /ha1588/trunk/rtl/top/
25 Updated SOPC Builder component and example system. edn_walter 4596d 05h /ha1588/trunk/rtl/top/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4598d 01h /ha1588/trunk/rtl/top/
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 4602d 05h /ha1588/trunk/rtl/top/
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4602d 06h /ha1588/trunk/rtl/top/
17 Updated reg.v content. edn_walter 4602d 23h /ha1588/trunk/rtl/top/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4609d 01h /ha1588/trunk/rtl/top/

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