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[/] [ha1588/] [trunk/] [sim/] - Rev 40

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39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4451d 15h /ha1588/trunk/sim/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4452d 12h /ha1588/trunk/sim/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4452d 16h /ha1588/trunk/sim/
36 TSU testbench is now self-checking. Test result is reported at end of simulation. edn_walter 4453d 11h /ha1588/trunk/sim/
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4454d 10h /ha1588/trunk/sim/
34 Added LGPL file header to all copyrighted files. edn_walter 4454d 13h /ha1588/trunk/sim/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4454d 14h /ha1588/trunk/sim/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4454d 16h /ha1588/trunk/sim/
31 Added hand-shaking for the TSU data reading. edn_walter 4455d 10h /ha1588/trunk/sim/
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4455d 10h /ha1588/trunk/sim/
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4455d 10h /ha1588/trunk/sim/
26 Updated test case. edn_walter 4457d 11h /ha1588/trunk/sim/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4458d 11h /ha1588/trunk/sim/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4459d 05h /ha1588/trunk/sim/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4459d 10h /ha1588/trunk/sim/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4460d 06h /ha1588/trunk/sim/
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4464d 10h /ha1588/trunk/sim/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4471d 06h /ha1588/trunk/sim/
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 4473d 06h /ha1588/trunk/sim/
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 4474d 06h /ha1588/trunk/sim/

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