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[/] [ha1588/] [trunk/] [sim/] - Rev 43

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Rev	Log message	Author	Age	Path
43	Added software configurable PTP message id mask for TSU parser.	edn_walter	4460d 01h	/ha1588/trunk/sim/
42	Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time.	edn_walter	4460d 07h	/ha1588/trunk/sim/
41	Added pre-adder to the accumulator to cut down critical timing path.	edn_walter	4460d 09h	/ha1588/trunk/sim/
39	1. Added memory map and feature description. 2. Separated TX RX TSU register addresses.	edn_walter	4460d 12h	/ha1588/trunk/sim/
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4461d 10h	/ha1588/trunk/sim/
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4461d 13h	/ha1588/trunk/sim/
36	TSU testbench is now self-checking. Test result is reported at end of simulation.	edn_walter	4462d 08h	/ha1588/trunk/sim/
35	Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets.	edn_walter	4463d 07h	/ha1588/trunk/sim/
34	Added LGPL file header to all copyrighted files.	edn_walter	4463d 10h	/ha1588/trunk/sim/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4463d 11h	/ha1588/trunk/sim/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4463d 14h	/ha1588/trunk/sim/
31	Added hand-shaking for the TSU data reading.	edn_walter	4464d 07h	/ha1588/trunk/sim/
30	Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit	edn_walter	4464d 07h	/ha1588/trunk/sim/
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4464d 07h	/ha1588/trunk/sim/
26	Updated test case.	edn_walter	4466d 08h	/ha1588/trunk/sim/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4467d 09h	/ha1588/trunk/sim/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4468d 03h	/ha1588/trunk/sim/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4468d 07h	/ha1588/trunk/sim/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4469d 03h	/ha1588/trunk/sim/
19	Added pipeline registers to Real Time Clock module to improve timing.	edn_walter	4473d 08h	/ha1588/trunk/sim/

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[/] [ha1588/] [trunk/] [sim/] - Rev 43

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