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[/] [ha1588/] [trunk/] [sim/] [rtc/] - Rev 38

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38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.
edn_walter 4485d 07h /ha1588/trunk/sim/rtc/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4485d 11h /ha1588/trunk/sim/rtc/
34 Added LGPL file header to all copyrighted files. edn_walter 4487d 08h /ha1588/trunk/sim/rtc/
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4497d 05h /ha1588/trunk/sim/rtc/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 4504d 01h /ha1588/trunk/sim/rtc/
3 Added function block RTC and its unit test. ash_riple 4522d 00h /ha1588/trunk/sim/rtc/

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