OpenCores
URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sim/] [rtc/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
69 Fixed the negative period adjustment bug. ash_riple 4160d 07h /ha1588/trunk/sim/rtc/
63 Updated the simulation script under Linux. ash_riple 4172d 08h /ha1588/trunk/sim/rtc/
62 Removed environment variable settings in the simulation script under Windows. ash_riple 4172d 08h /ha1588/trunk/sim/rtc/
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4445d 06h /ha1588/trunk/sim/rtc/
52 1. Corrected GMII BFM preamble+sfd size error: 4B 5555555d changed to 8B 5555555555555555d5.
2. Corrected packet parser 4B counter accordingly.		 edn_walter 4448d 03h /ha1588/trunk/sim/rtc/
47 Added test case of -16 negative period_adj value, to show the effect trying to set time backwards. Thanks to Frank Yang's question. edn_walter 4453d 13h /ha1588/trunk/sim/rtc/
42 Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. edn_walter 4458d 02h /ha1588/trunk/sim/rtc/
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4458d 04h /ha1588/trunk/sim/rtc/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4459d 05h /ha1588/trunk/sim/rtc/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4459d 08h /ha1588/trunk/sim/rtc/
34 Added LGPL file header to all copyrighted files. edn_walter 4461d 05h /ha1588/trunk/sim/rtc/
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4471d 03h /ha1588/trunk/sim/rtc/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4477d 22h /ha1588/trunk/sim/rtc/
3 Added function block RTC and its unit test. ash_riple 4495d 21h /ha1588/trunk/sim/rtc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.