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[/] [ha1588/] [trunk/] [sim/] [top/] - Rev 37

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37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4460d 11h /ha1588/trunk/sim/top/
34 Added LGPL file header to all copyrighted files. edn_walter 4462d 08h /ha1588/trunk/sim/top/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4462d 09h /ha1588/trunk/sim/top/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4462d 12h /ha1588/trunk/sim/top/
31 Added hand-shaking for the TSU data reading. edn_walter 4463d 05h /ha1588/trunk/sim/top/
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4463d 05h /ha1588/trunk/sim/top/
26 Updated test case. edn_walter 4465d 06h /ha1588/trunk/sim/top/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4466d 07h /ha1588/trunk/sim/top/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4467d 01h /ha1588/trunk/sim/top/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4467d 05h /ha1588/trunk/sim/top/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4468d 01h /ha1588/trunk/sim/top/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4479d 01h /ha1588/trunk/sim/top/

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