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[/] [ha1588/] [trunk/] [sim/] [top/] - Rev 47

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46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4471d 19h /ha1588/trunk/sim/top/
44 Updated TSU testbench. edn_walter 4472d 13h /ha1588/trunk/sim/top/
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4473d 11h /ha1588/trunk/sim/top/
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4473d 22h /ha1588/trunk/sim/top/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4474d 20h /ha1588/trunk/sim/top/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4474d 23h /ha1588/trunk/sim/top/
34 Added LGPL file header to all copyrighted files. edn_walter 4476d 20h /ha1588/trunk/sim/top/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4476d 21h /ha1588/trunk/sim/top/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4476d 23h /ha1588/trunk/sim/top/
31 Added hand-shaking for the TSU data reading. edn_walter 4477d 17h /ha1588/trunk/sim/top/
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4477d 17h /ha1588/trunk/sim/top/
26 Updated test case. edn_walter 4479d 18h /ha1588/trunk/sim/top/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4480d 19h /ha1588/trunk/sim/top/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4481d 13h /ha1588/trunk/sim/top/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4481d 17h /ha1588/trunk/sim/top/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4482d 13h /ha1588/trunk/sim/top/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4493d 13h /ha1588/trunk/sim/top/

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