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[/] [ha1588/] [trunk/] [sim/] [top/] - Rev 74

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Rev	Log message	Author	Age	Path
68	Refined the vendor specific IP instanttiation. Now DCFIFO is instantiated as a vendor specific IP in PAR directory.	ash_riple	4160d 10h	/ha1588/trunk/sim/top/
62	Removed environment variable settings in the simulation script under Windows.	ash_riple	4172d 08h	/ha1588/trunk/sim/top/
61	Made different scripts for top-level simulation to run under Linux.	ash_riple	4172d 09h	/ha1588/trunk/sim/top/
60	Made different scripts for top-level simulation to run under Linux.	ash_riple	4172d 09h	/ha1588/trunk/sim/top/
59	Made different scripts for top-level simulation to run under Windows.	ash_riple	4172d 09h	/ha1588/trunk/sim/top/
58	Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s.	edn_walter	4445d 06h	/ha1588/trunk/sim/top/
54	Added support for MII interface as well as GMII interface. Updated unit and top-level test cases.	edn_walter	4446d 04h	/ha1588/trunk/sim/top/
52	1. Corrected GMII BFM preamble+sfd size error: 4B 5555555d changed to 8B 5555555555555555d5. 2. Corrected packet parser 4B counter accordingly.	edn_walter	4448d 02h	/ha1588/trunk/sim/top/
46	Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c.	edn_walter	4456d 04h	/ha1588/trunk/sim/top/
44	Updated TSU testbench.	edn_walter	4456d 22h	/ha1588/trunk/sim/top/
43	Added software configurable PTP message id mask for TSU parser.	edn_walter	4457d 20h	/ha1588/trunk/sim/top/
39	1. Added memory map and feature description. 2. Separated TX RX TSU register addresses.	edn_walter	4458d 07h	/ha1588/trunk/sim/top/
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4459d 05h	/ha1588/trunk/sim/top/
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4459d 08h	/ha1588/trunk/sim/top/
34	Added LGPL file header to all copyrighted files.	edn_walter	4461d 05h	/ha1588/trunk/sim/top/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4461d 06h	/ha1588/trunk/sim/top/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4461d 09h	/ha1588/trunk/sim/top/
31	Added hand-shaking for the TSU data reading.	edn_walter	4462d 02h	/ha1588/trunk/sim/top/
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4462d 02h	/ha1588/trunk/sim/top/
26	Updated test case.	edn_walter	4464d 03h	/ha1588/trunk/sim/top/

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[/] [ha1588/] [trunk/] [sim/] [top/] - Rev 74

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