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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] - Rev 37

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37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4478d 19h /ha1588/trunk/sim/top/ptp_drv_bfm/
34 Added LGPL file header to all copyrighted files. edn_walter 4480d 16h /ha1588/trunk/sim/top/ptp_drv_bfm/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4480d 17h /ha1588/trunk/sim/top/ptp_drv_bfm/
31 Added hand-shaking for the TSU data reading. edn_walter 4481d 13h /ha1588/trunk/sim/top/ptp_drv_bfm/
26 Updated test case. edn_walter 4483d 15h /ha1588/trunk/sim/top/ptp_drv_bfm/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4484d 15h /ha1588/trunk/sim/top/ptp_drv_bfm/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4485d 09h /ha1588/trunk/sim/top/ptp_drv_bfm/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4485d 13h /ha1588/trunk/sim/top/ptp_drv_bfm/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4486d 10h /ha1588/trunk/sim/top/ptp_drv_bfm/

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