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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] - Rev 44

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44 Updated TSU testbench. edn_walter 4507d 04h /ha1588/trunk/sim/top/ptp_drv_bfm/
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4508d 01h /ha1588/trunk/sim/top/ptp_drv_bfm/
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4508d 13h /ha1588/trunk/sim/top/ptp_drv_bfm/
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4509d 10h /ha1588/trunk/sim/top/ptp_drv_bfm/
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4509d 14h /ha1588/trunk/sim/top/ptp_drv_bfm/
34 Added LGPL file header to all copyrighted files. edn_walter 4511d 10h /ha1588/trunk/sim/top/ptp_drv_bfm/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4511d 12h /ha1588/trunk/sim/top/ptp_drv_bfm/
31 Added hand-shaking for the TSU data reading. edn_walter 4512d 08h /ha1588/trunk/sim/top/ptp_drv_bfm/
26 Updated test case. edn_walter 4514d 09h /ha1588/trunk/sim/top/ptp_drv_bfm/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4515d 09h /ha1588/trunk/sim/top/ptp_drv_bfm/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4516d 03h /ha1588/trunk/sim/top/ptp_drv_bfm/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4516d 07h /ha1588/trunk/sim/top/ptp_drv_bfm/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4517d 04h /ha1588/trunk/sim/top/ptp_drv_bfm/

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