URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_2/] - Rev 14

Rev	Log message	Author	Age	Path
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8258d 22h	/i2c/tags/asyst_2/
13	Fixed some synthesis warnings.	rherveille	8270d 02h	/i2c/tags/asyst_2/
12	no message	rherveille	8275d 18h	/i2c/tags/asyst_2/
11	Changed RST_LVL define to parameter.	rherveille	8279d 01h	/i2c/tags/asyst_2/
10	Created new directory structure. Added Verilog version.	rherveille	8300d 22h	/i2c/tags/asyst_2/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8370d 17h	/i2c/tags/asyst_2/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8370d 17h	/i2c/tags/asyst_2/
7	added some remarks, fixed some sensitivity lists	rherveille	8439d 20h	/i2c/tags/asyst_2/
6	fixed typo txt -> txr	rherveille	8444d 00h	/i2c/tags/asyst_2/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8450d 22h	/i2c/tags/asyst_2/
4	WISHBONE I2C Master Core: initial release	rherveille	8503d 01h	/i2c/tags/asyst_2/
2	initial release	rherveille	8565d 00h	/i2c/tags/asyst_2/
1	Standard project directories initialized by cvs2svn.		8565d 00h	/i2c/tags/asyst_2/