URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_2/] - Rev 16

Rev	Log message	Author	Age	Path
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8307d 02h	/i2c/tags/asyst_2/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8312d 01h	/i2c/tags/asyst_2/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8312d 01h	/i2c/tags/asyst_2/
13	Fixed some synthesis warnings.	rherveille	8323d 05h	/i2c/tags/asyst_2/
12	no message	rherveille	8328d 21h	/i2c/tags/asyst_2/
11	Changed RST_LVL define to parameter.	rherveille	8332d 04h	/i2c/tags/asyst_2/
10	Created new directory structure. Added Verilog version.	rherveille	8354d 01h	/i2c/tags/asyst_2/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8423d 20h	/i2c/tags/asyst_2/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8423d 20h	/i2c/tags/asyst_2/
7	added some remarks, fixed some sensitivity lists	rherveille	8492d 23h	/i2c/tags/asyst_2/
6	fixed typo txt -> txr	rherveille	8497d 02h	/i2c/tags/asyst_2/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8504d 01h	/i2c/tags/asyst_2/
4	WISHBONE I2C Master Core: initial release	rherveille	8556d 04h	/i2c/tags/asyst_2/
2	initial release	rherveille	8618d 03h	/i2c/tags/asyst_2/
1	Standard project directories initialized by cvs2svn.		8618d 03h	/i2c/tags/asyst_2/