OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_2/] - Rev 18

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 no message rherveille 8179d 13h /i2c/tags/asyst_2/
17 C-include file.
Initial release		 rherveille 8267d 18h /i2c/tags/asyst_2/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8279d 17h /i2c/tags/asyst_2/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8284d 16h /i2c/tags/asyst_2/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8284d 16h /i2c/tags/asyst_2/
13 Fixed some synthesis warnings. rherveille 8295d 20h /i2c/tags/asyst_2/
12 no message rherveille 8301d 12h /i2c/tags/asyst_2/
11 Changed RST_LVL define to parameter. rherveille 8304d 19h /i2c/tags/asyst_2/
10 Created new directory structure.
Added Verilog version.		 rherveille 8326d 16h /i2c/tags/asyst_2/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8396d 11h /i2c/tags/asyst_2/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8396d 11h /i2c/tags/asyst_2/
7 added some remarks, fixed some sensitivity lists rherveille 8465d 14h /i2c/tags/asyst_2/
6 fixed typo txt -> txr rherveille 8469d 17h /i2c/tags/asyst_2/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8476d 15h /i2c/tags/asyst_2/
4 WISHBONE I2C Master Core: initial release rherveille 8528d 19h /i2c/tags/asyst_2/
2 initial release rherveille 8590d 18h /i2c/tags/asyst_2/
1 Standard project directories initialized by cvs2svn. 8590d 18h /i2c/tags/asyst_2/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.