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[/] [i2c/] [tags/] [asyst_2/] - Rev 35

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Rev Log message Author Age Path
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7815d 21h /i2c/tags/asyst_2/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7819d 19h /i2c/tags/asyst_2/
33 Fixed a bug in the Command Register declaration. rherveille 7842d 04h /i2c/tags/asyst_2/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7852d 03h /i2c/tags/asyst_2/
31 Core is now a Multimaster I2C controller. rherveille 7856d 05h /i2c/tags/asyst_2/
30 Small code simplifications rherveille 7856d 05h /i2c/tags/asyst_2/
29 Core is now a Multimaster I2C controller rherveille 7856d 06h /i2c/tags/asyst_2/
28 *** empty log message *** rherveille 7881d 22h /i2c/tags/asyst_2/
27 Cleaned up code rherveille 7881d 22h /i2c/tags/asyst_2/
26 *** empty log message *** rherveille 7885d 06h /i2c/tags/asyst_2/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7913d 02h /i2c/tags/asyst_2/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7913d 02h /i2c/tags/asyst_2/
23 *** empty log message *** rherveille 8040d 08h /i2c/tags/asyst_2/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8050d 13h /i2c/tags/asyst_2/
21 no message rherveille 8136d 14h /i2c/tags/asyst_2/
20 Added Appendix A rherveille 8136d 14h /i2c/tags/asyst_2/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8140d 10h /i2c/tags/asyst_2/
18 no message rherveille 8167d 06h /i2c/tags/asyst_2/
17 C-include file.
Initial release		 rherveille 8255d 11h /i2c/tags/asyst_2/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8267d 10h /i2c/tags/asyst_2/

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