URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 24

Rev	Log message	Author	Age	Path
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7897d 22h	/i2c/tags/asyst_2/rtl/verilog/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8035d 09h	/i2c/tags/asyst_2/rtl/verilog/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8252d 06h	/i2c/tags/asyst_2/rtl/verilog/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8257d 05h	/i2c/tags/asyst_2/rtl/verilog/
13	Fixed some synthesis warnings.	rherveille	8268d 09h	/i2c/tags/asyst_2/rtl/verilog/
11	Changed RST_LVL define to parameter.	rherveille	8277d 08h	/i2c/tags/asyst_2/rtl/verilog/
10	Created new directory structure. Added Verilog version.	rherveille	8299d 04h	/i2c/tags/asyst_2/rtl/verilog/