URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] - Rev 10

Rev	Log message	Author	Age	Path
10	Created new directory structure. Added Verilog version.	rherveille	8290d 06h	/i2c/tags/asyst_3/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8360d 01h	/i2c/tags/asyst_3/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8360d 01h	/i2c/tags/asyst_3/
7	added some remarks, fixed some sensitivity lists	rherveille	8429d 04h	/i2c/tags/asyst_3/
6	fixed typo txt -> txr	rherveille	8433d 08h	/i2c/tags/asyst_3/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8440d 06h	/i2c/tags/asyst_3/
4	WISHBONE I2C Master Core: initial release	rherveille	8492d 09h	/i2c/tags/asyst_3/
2	initial release	rherveille	8554d 08h	/i2c/tags/asyst_3/
1	Standard project directories initialized by cvs2svn.		8554d 08h	/i2c/tags/asyst_3/