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[/] [i2c/] [tags/] [asyst_3/] - Rev 35

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Rev Log message Author Age Path
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7796d 19h /i2c/tags/asyst_3/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7800d 17h /i2c/tags/asyst_3/
33 Fixed a bug in the Command Register declaration. rherveille 7823d 02h /i2c/tags/asyst_3/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7833d 01h /i2c/tags/asyst_3/
31 Core is now a Multimaster I2C controller. rherveille 7837d 03h /i2c/tags/asyst_3/
30 Small code simplifications rherveille 7837d 03h /i2c/tags/asyst_3/
29 Core is now a Multimaster I2C controller rherveille 7837d 04h /i2c/tags/asyst_3/
28 *** empty log message *** rherveille 7862d 20h /i2c/tags/asyst_3/
27 Cleaned up code rherveille 7862d 20h /i2c/tags/asyst_3/
26 *** empty log message *** rherveille 7866d 04h /i2c/tags/asyst_3/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7894d 00h /i2c/tags/asyst_3/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7894d 00h /i2c/tags/asyst_3/
23 *** empty log message *** rherveille 8021d 06h /i2c/tags/asyst_3/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8031d 11h /i2c/tags/asyst_3/
21 no message rherveille 8117d 12h /i2c/tags/asyst_3/
20 Added Appendix A rherveille 8117d 12h /i2c/tags/asyst_3/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8121d 08h /i2c/tags/asyst_3/
18 no message rherveille 8148d 04h /i2c/tags/asyst_3/
17 C-include file.
Initial release		 rherveille 8236d 09h /i2c/tags/asyst_3/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8248d 08h /i2c/tags/asyst_3/

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