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[/] [i2c/] [tags/] [asyst_3/] [rtl/] - Rev 15

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Rev Log message Author Age Path
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8260d 03h /i2c/tags/asyst_3/rtl/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8260d 03h /i2c/tags/asyst_3/rtl/
13 Fixed some synthesis warnings. rherveille 8271d 07h /i2c/tags/asyst_3/rtl/
11 Changed RST_LVL define to parameter. rherveille 8280d 06h /i2c/tags/asyst_3/rtl/
10 Created new directory structure.
Added Verilog version.
rherveille 8302d 03h /i2c/tags/asyst_3/rtl/

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