URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] - Rev 10

Rev	Log message	Author	Age	Path
10	Created new directory structure. Added Verilog version.	rherveille	8277d 02h	/i2c/tags/rel_1/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8346d 21h	/i2c/tags/rel_1/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8346d 22h	/i2c/tags/rel_1/
7	added some remarks, fixed some sensitivity lists	rherveille	8416d 00h	/i2c/tags/rel_1/
6	fixed typo txt -> txr	rherveille	8420d 04h	/i2c/tags/rel_1/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8427d 02h	/i2c/tags/rel_1/
4	WISHBONE I2C Master Core: initial release	rherveille	8479d 05h	/i2c/tags/rel_1/
2	initial release	rherveille	8541d 05h	/i2c/tags/rel_1/
1	Standard project directories initialized by cvs2svn.		8541d 05h	/i2c/tags/rel_1/