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[/] [i2c/] [tags/] [rel_1/] - Rev 12

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Rev Log message Author Age Path
12 no message rherveille 8276d 01h /i2c/tags/rel_1/
11 Changed RST_LVL define to parameter. rherveille 8279d 09h /i2c/tags/rel_1/
10 Created new directory structure.
Added Verilog version.		 rherveille 8301d 05h /i2c/tags/rel_1/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8371d 00h /i2c/tags/rel_1/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8371d 00h /i2c/tags/rel_1/
7 added some remarks, fixed some sensitivity lists rherveille 8440d 03h /i2c/tags/rel_1/
6 fixed typo txt -> txr rherveille 8444d 07h /i2c/tags/rel_1/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8451d 05h /i2c/tags/rel_1/
4 WISHBONE I2C Master Core: initial release rherveille 8503d 08h /i2c/tags/rel_1/
2 initial release rherveille 8565d 07h /i2c/tags/rel_1/
1 Standard project directories initialized by cvs2svn. 8565d 07h /i2c/tags/rel_1/

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