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[/] [i2c/] [tags/] [rel_1/] - Rev 26

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Rev Log message Author Age Path
26 *** empty log message *** rherveille 7849d 08h /i2c/tags/rel_1/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7877d 04h /i2c/tags/rel_1/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7877d 04h /i2c/tags/rel_1/
23 *** empty log message *** rherveille 8004d 10h /i2c/tags/rel_1/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8014d 15h /i2c/tags/rel_1/
21 no message rherveille 8100d 15h /i2c/tags/rel_1/
20 Added Appendix A rherveille 8100d 15h /i2c/tags/rel_1/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8104d 12h /i2c/tags/rel_1/
18 no message rherveille 8131d 08h /i2c/tags/rel_1/
17 C-include file.
Initial release		 rherveille 8219d 12h /i2c/tags/rel_1/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8231d 11h /i2c/tags/rel_1/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8236d 10h /i2c/tags/rel_1/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8236d 10h /i2c/tags/rel_1/
13 Fixed some synthesis warnings. rherveille 8247d 14h /i2c/tags/rel_1/
12 no message rherveille 8253d 06h /i2c/tags/rel_1/
11 Changed RST_LVL define to parameter. rherveille 8256d 13h /i2c/tags/rel_1/
10 Created new directory structure.
Added Verilog version.		 rherveille 8278d 10h /i2c/tags/rel_1/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8348d 05h /i2c/tags/rel_1/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8348d 05h /i2c/tags/rel_1/
7 added some remarks, fixed some sensitivity lists rherveille 8417d 08h /i2c/tags/rel_1/

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