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[/] [i2c/] [tags/] [rel_1/] - Rev 32

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32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7827d 13h /i2c/tags/rel_1/
31 Core is now a Multimaster I2C controller. rherveille 7831d 15h /i2c/tags/rel_1/
30 Small code simplifications rherveille 7831d 15h /i2c/tags/rel_1/
29 Core is now a Multimaster I2C controller rherveille 7831d 16h /i2c/tags/rel_1/
28 *** empty log message *** rherveille 7857d 08h /i2c/tags/rel_1/
27 Cleaned up code rherveille 7857d 08h /i2c/tags/rel_1/
26 *** empty log message *** rherveille 7860d 16h /i2c/tags/rel_1/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7888d 13h /i2c/tags/rel_1/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7888d 13h /i2c/tags/rel_1/
23 *** empty log message *** rherveille 8015d 18h /i2c/tags/rel_1/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8025d 23h /i2c/tags/rel_1/
21 no message rherveille 8112d 00h /i2c/tags/rel_1/
20 Added Appendix A rherveille 8112d 00h /i2c/tags/rel_1/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8115d 20h /i2c/tags/rel_1/
18 no message rherveille 8142d 16h /i2c/tags/rel_1/
17 C-include file.
Initial release		 rherveille 8230d 21h /i2c/tags/rel_1/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8242d 20h /i2c/tags/rel_1/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8247d 19h /i2c/tags/rel_1/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8247d 19h /i2c/tags/rel_1/
13 Fixed some synthesis warnings. rherveille 8258d 23h /i2c/tags/rel_1/

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