URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 30

Rev	Log message	Author	Age	Path
30	Small code simplifications	rherveille	7848d 19h	/i2c/tags/rel_1/rtl/verilog/
29	Core is now a Multimaster I2C controller	rherveille	7848d 20h	/i2c/tags/rel_1/rtl/verilog/
27	Cleaned up code	rherveille	7874d 12h	/i2c/tags/rel_1/rtl/verilog/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7905d 16h	/i2c/tags/rel_1/rtl/verilog/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8043d 03h	/i2c/tags/rel_1/rtl/verilog/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8260d 00h	/i2c/tags/rel_1/rtl/verilog/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8264d 23h	/i2c/tags/rel_1/rtl/verilog/
13	Fixed some synthesis warnings.	rherveille	8276d 03h	/i2c/tags/rel_1/rtl/verilog/
11	Changed RST_LVL define to parameter.	rherveille	8285d 02h	/i2c/tags/rel_1/rtl/verilog/
10	Created new directory structure. Added Verilog version.	rherveille	8306d 22h	/i2c/tags/rel_1/rtl/verilog/