URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [rtl/] [vhdl/] - Rev 27

Rev	Log message	Author	Age	Path
27	Cleaned up code	rherveille	7856d 23h	/i2c/tags/rel_1/rtl/vhdl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7888d 03h	/i2c/tags/rel_1/rtl/vhdl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8025d 14h	/i2c/tags/rel_1/rtl/vhdl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8242d 11h	/i2c/tags/rel_1/rtl/vhdl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8247d 10h	/i2c/tags/rel_1/rtl/vhdl/
10	Created new directory structure. Added Verilog version.	rherveille	8289d 09h	/i2c/tags/rel_1/rtl/vhdl/