URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 23

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Rev	Log message	Author	Age	Path
23	* empty log message *	rherveille	8021d 00h	/i2c/trunk/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8031d 05h	/i2c/trunk/
21	no message	rherveille	8117d 06h	/i2c/trunk/
20	Added Appendix A	rherveille	8117d 06h	/i2c/trunk/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8121d 03h	/i2c/trunk/
18	no message	rherveille	8147d 22h	/i2c/trunk/
17	C-include file. Initial release	rherveille	8236d 03h	/i2c/trunk/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8248d 02h	/i2c/trunk/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8253d 01h	/i2c/trunk/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8253d 01h	/i2c/trunk/
13	Fixed some synthesis warnings.	rherveille	8264d 05h	/i2c/trunk/
12	no message	rherveille	8269d 21h	/i2c/trunk/
11	Changed RST_LVL define to parameter.	rherveille	8273d 04h	/i2c/trunk/
10	Created new directory structure. Added Verilog version.	rherveille	8295d 01h	/i2c/trunk/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8364d 20h	/i2c/trunk/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8364d 20h	/i2c/trunk/
7	added some remarks, fixed some sensitivity lists	rherveille	8433d 23h	/i2c/trunk/
6	fixed typo txt -> txr	rherveille	8438d 02h	/i2c/trunk/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8445d 00h	/i2c/trunk/
4	WISHBONE I2C Master Core: initial release	rherveille	8497d 04h	/i2c/trunk/

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Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 23

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