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[/] [i2c/] [trunk/] [rtl/] [verilog/] - Rev 57

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Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6495d 06h /i2c/trunk/rtl/verilog/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7049d 06h /i2c/trunk/rtl/verilog/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7345d 04h /i2c/trunk/rtl/verilog/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7424d 04h /i2c/trunk/rtl/verilog/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7594d 05h /i2c/trunk/rtl/verilog/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7617d 08h /i2c/trunk/rtl/verilog/
36 Fixed cmd_ack generation item (no bug). rherveille 7769d 01h /i2c/trunk/rtl/verilog/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7802d 15h /i2c/trunk/rtl/verilog/
33 Fixed a bug in the Command Register declaration. rherveille 7828d 22h /i2c/trunk/rtl/verilog/
30 Small code simplifications rherveille 7842d 23h /i2c/trunk/rtl/verilog/
29 Core is now a Multimaster I2C controller rherveille 7843d 00h /i2c/trunk/rtl/verilog/
27 Cleaned up code rherveille 7868d 17h /i2c/trunk/rtl/verilog/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7899d 21h /i2c/trunk/rtl/verilog/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8037d 08h /i2c/trunk/rtl/verilog/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8254d 04h /i2c/trunk/rtl/verilog/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8259d 03h /i2c/trunk/rtl/verilog/
13 Fixed some synthesis warnings. rherveille 8270d 07h /i2c/trunk/rtl/verilog/
11 Changed RST_LVL define to parameter. rherveille 8279d 06h /i2c/trunk/rtl/verilog/
10 Created new directory structure.
Added Verilog version.		 rherveille 8301d 03h /i2c/trunk/rtl/verilog/

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