URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] - Rev 102

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Rev	Log message	Author	Age	Path
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4863d 03h	/ion/
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4863d 03h	/ion/
100	Obsolete synthesizable template files removed	ja_rd	4887d 12h	/ion/
99	Obsolete TB template files removed	ja_rd	4887d 12h	/ion/
98	CPU rd and wr data address buses unified	ja_rd	4887d 12h	/ion/
97	CPU rd and wr data address buses unified	ja_rd	4887d 12h	/ion/
96	CPU rd and wr data address buses unified	ja_rd	4887d 12h	/ion/
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4898d 08h	/ion/
94	Pregenerated demo 'hello' files updated	ja_rd	4898d 08h	/ion/
93	SW simulator supports 'log trigger address' and keyboard input as simulated UART RX. Project parameters now launch adventure demo automatically	ja_rd	4898d 08h	/ion/
92	'hello' demo updated to use new startup files	ja_rd	4898d 08h	/ion/
91	FIX: startup files can now be used to run from FLASH or BRAM	ja_rd	4898d 08h	/ion/
90	Added 'Adventure' demo to be run from the DE-1 FLASH	ja_rd	4898d 09h	/ion/
89	Added startup and utility functions for 'bare metal' applications running from FLASH, plus linker file	ja_rd	4898d 09h	/ion/
88	Added UART RX interface to MPU template	ja_rd	4898d 09h	/ion/
87	Added UART RX interface to MPU template	ja_rd	4898d 09h	/ion/
86	Adapted TB template to use log trigger address	ja_rd	4898d 09h	/ion/
85	BUG FIX: log2 function was wrong	ja_rd	4898d 09h	/ion/
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	4898d 09h	/ion/
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	4898d 09h	/ion/

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Subversion Repositories ion

[/] [ion/] - Rev 102

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