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Rev Log message Author Age Path
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)
ja_rd 4854d 12h /ion/
112 Updated simulation package for compatibility to new cache ja_rd 4854d 12h /ion/
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4854d 12h /ion/
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4854d 12h /ion/
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation
ja_rd 4854d 12h /ion/
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)
ja_rd 4854d 13h /ion/
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code
ja_rd 4858d 11h /ion/
106 SW samples updated:
- Added batch files for running the SW simulation
ja_rd 4858d 12h /ion/
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux
ja_rd 4858d 12h /ion/
104 FIXED typo in last commit for simulation template ja_rd 4863d 02h /ion/
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4863d 03h /ion/
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4863d 03h /ion/
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4863d 03h /ion/
100 Obsolete synthesizable template files removed ja_rd 4887d 12h /ion/
99 Obsolete TB template files removed ja_rd 4887d 12h /ion/
98 CPU rd and wr data address buses unified ja_rd 4887d 12h /ion/
97 CPU rd and wr data address buses unified ja_rd 4887d 12h /ion/
96 CPU rd and wr data address buses unified ja_rd 4887d 12h /ion/
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4898d 08h /ion/
94 Pregenerated demo 'hello' files updated ja_rd 4898d 08h /ion/

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