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Rev Log message Author Age Path
226 Updated demo and test bench to use new SoC entity. ja_rd 4421d 14h /ion/
225 Added utility functions for the initialization of BRAM memories. ja_rd 4421d 14h /ion/
224 MCU entity gutted and transformed into a SoC entity
Different UART, new generics...
ja_rd 4421d 14h /ion/
223 MCU entity renamed to SoC, moved to separate SoC directory ja_rd 4421d 14h /ion/
222 Documentation updated ja_rd 4421d 15h /ion/
221 Documentation updated ja_rd 4421d 15h /ion/
220 New script for configuration package generation.
New directory for all utility scripts
ja_rd 4422d 00h /ion/
219 Added windows binary for MIPS simulator 'slite' to the SVN repo, for convenience. ja_rd 4422d 07h /ion/
218 UART bug fix: rx_rdy flag must be clear only when reading the rx buffer ja_rd 4425d 13h /ion/
217 Removed another SoC file prematurely committed ja_rd 4432d 04h /ion/
216 First draft of SoC removed.
I'll rename it from mips_mcu in order to keep the svn log.
ja_rd 4432d 04h /ion/
215 First draft of MIPS SoC
Still unused by any of the code samples.
Eventually will replace the mips_mcu entity
ja_rd 4432d 04h /ion/
214 Updated pre-generated 'Hello' demo, recompiled and retested with the latest changes. ja_rd 4432d 13h /ion/
213 Memory test application updated -- added extra-simple D-Cache test.
The new test is a row of back-to-back I/O reads and writes.
This test triggers a bug in the cache that has been already fixed.
ja_rd 4432d 13h /ion/
212 BUG FIX: sequences of back-to-back I/O reads or writes didn't work.
The stall conditions were wrong for those cases.
Minor cleanup of the comments
ja_rd 4432d 13h /ion/
211 Included a simulated block of I/O regs in the test bench for easing some cache tests. ja_rd 4432d 13h /ion/
210 Added new Tex sources
New doc sources organized according to Tex guidelines
ja_rd 4612d 00h /ion/
209 Documentation reorganization
Updated PDF committed
Old Tex sources removed
Old plain text file removed
ja_rd 4612d 00h /ion/
208 Bug fix in SW simulator
Crashed when a function call trace log was requested with missing map file
ja_rd 4698d 06h /ion/
207 Simulation memories now modelled with shared variables and not signals.
This improves simulation speed of large programs (e.g. Adventure) by orders of magnitude
ja_rd 4711d 09h /ion/

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