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Rev Log message Author Age Path
96 CPU rd and wr data address buses unified ja_rd 4887d 15h /ion/
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4898d 11h /ion/
94 Pregenerated demo 'hello' files updated ja_rd 4898d 11h /ion/
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically		 ja_rd 4898d 11h /ion/
92 'hello' demo updated to use new startup files ja_rd 4898d 12h /ion/
91 FIX: startup files can now be used to run from FLASH or BRAM ja_rd 4898d 12h /ion/
90 Added 'Adventure' demo to be run from the DE-1 FLASH ja_rd 4898d 12h /ion/
89 Added startup and utility functions for 'bare metal' applications running from FLASH, plus linker file ja_rd 4898d 12h /ion/
88 Added UART RX interface to MPU template ja_rd 4898d 12h /ion/
87 Added UART RX interface to MPU template ja_rd 4898d 12h /ion/
86 Adapted TB template to use log trigger address ja_rd 4898d 12h /ion/
85 BUG FIX: log2 function was wrong ja_rd 4898d 12h /ion/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4898d 12h /ion/
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong		 ja_rd 4898d 12h /ion/
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4900d 12h /ion/
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4907d 07h /ion/
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 4907d 07h /ion/
79 modelsim wave window script updated ja_rd 4908d 08h /ion/
78 Code sample 'memtest' adapted to test read from flash ja_rd 4908d 09h /ion/
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 4908d 09h /ion/

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