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[/] [ion/] [trunk/] - Rev 118

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Rev Log message Author Age Path
118 Updates sim scripts to include new cache ja_rd 4836d 06h /ion/trunk/
117 Updated project doc (still not fully up to date) ja_rd 4836d 07h /ion/trunk/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4836d 07h /ion/trunk/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4836d 09h /ion/trunk/
114 ADDED: 1st version of real cache ja_rd 4836d 10h /ion/trunk/
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)
ja_rd 4836d 11h /ion/trunk/
112 Updated simulation package for compatibility to new cache ja_rd 4836d 11h /ion/trunk/
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4836d 11h /ion/trunk/
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4836d 11h /ion/trunk/
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation
ja_rd 4836d 11h /ion/trunk/
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)
ja_rd 4836d 12h /ion/trunk/
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code
ja_rd 4840d 10h /ion/trunk/
106 SW samples updated:
- Added batch files for running the SW simulation
ja_rd 4840d 11h /ion/trunk/
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux
ja_rd 4840d 11h /ion/trunk/
104 FIXED typo in last commit for simulation template ja_rd 4845d 01h /ion/trunk/
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4845d 02h /ion/trunk/
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4845d 02h /ion/trunk/
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4845d 02h /ion/trunk/
100 Obsolete synthesizable template files removed ja_rd 4869d 11h /ion/trunk/
99 Obsolete TB template files removed ja_rd 4869d 11h /ion/trunk/

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