OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] - Rev 136

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4778d 04h /ion/trunk/
135 Added debug output to synthesizable MPU template. ja_rd 4778d 04h /ion/trunk/
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4778d 04h /ion/trunk/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4781d 01h /ion/trunk/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4781d 01h /ion/trunk/
131 change to local system-dependent directory path ja_rd 4781d 01h /ion/trunk/
130 typo fix ja_rd 4781d 01h /ion/trunk/
129 updated pregenerated demo ('hello') ja_rd 4781d 01h /ion/trunk/
128 updated precompiled simulation testbench ja_rd 4781d 02h /ion/trunk/
127 added SDRAM verilog simulation model to sim script ja_rd 4781d 02h /ion/trunk/
126 added SDRAM verilog simulation model ja_rd 4781d 02h /ion/trunk/
125 MPU templates now use the real cache by default ja_rd 4781d 02h /ion/trunk/
124 Fixed typo in python script header comment ja_rd 4826d 07h /ion/trunk/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4826d 10h /ion/trunk/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4826d 10h /ion/trunk/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4827d 01h /ion/trunk/
120 Updated main package with lots of wait states for all areas ja_rd 4836d 04h /ion/trunk/
119 Updated pre-generated simulation and synthesis demos ja_rd 4836d 04h /ion/trunk/
118 Updates sim scripts to include new cache ja_rd 4836d 04h /ion/trunk/
117 Updated project doc (still not fully up to date) ja_rd 4836d 05h /ion/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.