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[/] [ion/] [trunk/] - Rev 138

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Rev Log message Author Age Path
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4824d 20h /ion/trunk/
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4824d 20h /ion/trunk/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4824d 21h /ion/trunk/
135 Added debug output to synthesizable MPU template. ja_rd 4824d 21h /ion/trunk/
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4824d 21h /ion/trunk/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4827d 18h /ion/trunk/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4827d 18h /ion/trunk/
131 change to local system-dependent directory path ja_rd 4827d 18h /ion/trunk/
130 typo fix ja_rd 4827d 18h /ion/trunk/
129 updated pregenerated demo ('hello') ja_rd 4827d 18h /ion/trunk/
128 updated precompiled simulation testbench ja_rd 4827d 18h /ion/trunk/
127 added SDRAM verilog simulation model to sim script ja_rd 4827d 18h /ion/trunk/
126 added SDRAM verilog simulation model ja_rd 4827d 18h /ion/trunk/
125 MPU templates now use the real cache by default ja_rd 4827d 19h /ion/trunk/
124 Fixed typo in python script header comment ja_rd 4873d 00h /ion/trunk/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4873d 03h /ion/trunk/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4873d 03h /ion/trunk/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4873d 18h /ion/trunk/
120 Updated main package with lots of wait states for all areas ja_rd 4882d 21h /ion/trunk/
119 Updated pre-generated simulation and synthesis demos ja_rd 4882d 21h /ion/trunk/

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