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[/] [ion/] [trunk/] - Rev 151

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Rev	Log message	Author	Age	Path
151	BUG FIX: major bugs fixed in cache module 1.- sram address was wrong (leftover from previous version) 2.- writes to unmapped areas were blocking the cache 3.- Sequence SW,LW produced a RAW data hazard in some cases	ja_rd	4780d 17h	/ion/trunk/
150	Bug fix: added missing nop in vacant branch delay slot	ja_rd	4781d 15h	/ion/trunk/
149	changed size of simulated flash in opcodes sample code	ja_rd	4781d 15h	/ion/trunk/
148	Added optional cache support to 'opcodes' test. Updated simulation length accordingly.	ja_rd	4783d 06h	/ion/trunk/
147	SW simulator updated to latest HW revision (plus a few mistakes corrected: wrongly commented out lines, mostly)	ja_rd	4783d 06h	/ion/trunk/
146	Added D-Cache setup code to 'adventure' bootstrap code (redundant since common C startup code already does it but...)	ja_rd	4783d 07h	/ion/trunk/
145	MAJOR UPDATE: first version of D-Cache	ja_rd	4783d 07h	/ion/trunk/
144	Added cache setup code to common startup code Important: the new cache won't work without this	ja_rd	4783d 07h	/ion/trunk/
143	'adventure' sample by default will log from 0xb0000000 and simulation length is now longer	ja_rd	4784d 21h	/ion/trunk/
142	'Adventure' bootstrap code now enables the cache (and runs noticeably faster on DE-1 board)	ja_rd	4784d 21h	/ion/trunk/
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4784d 21h	/ion/trunk/
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4784d 21h	/ion/trunk/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4785d 15h	/ion/trunk/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4785d 15h	/ion/trunk/
137	Updated TB2 for new cache interface ('unmapped' signal)	ja_rd	4785d 15h	/ion/trunk/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4785d 15h	/ion/trunk/
135	Added debug output to synthesizable MPU template.	ja_rd	4785d 15h	/ion/trunk/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4785d 15h	/ion/trunk/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4788d 12h	/ion/trunk/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4788d 13h	/ion/trunk/

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[/] [ion/] [trunk/] - Rev 151

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