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[/] [ion/] [trunk/] - Rev 89

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Rev Log message Author Age Path
89 Added startup and utility functions for 'bare metal' applications running from FLASH, plus linker file ja_rd 4895d 21h /ion/trunk/
88 Added UART RX interface to MPU template ja_rd 4895d 21h /ion/trunk/
87 Added UART RX interface to MPU template ja_rd 4895d 21h /ion/trunk/
86 Adapted TB template to use log trigger address ja_rd 4895d 21h /ion/trunk/
85 BUG FIX: log2 function was wrong ja_rd 4895d 21h /ion/trunk/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4895d 21h /ion/trunk/
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong		 ja_rd 4895d 21h /ion/trunk/
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4897d 21h /ion/trunk/
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4904d 16h /ion/trunk/
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 4904d 16h /ion/trunk/
79 modelsim wave window script updated ja_rd 4905d 17h /ion/trunk/
78 Code sample 'memtest' adapted to test read from flash ja_rd 4905d 18h /ion/trunk/
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 4905d 18h /ion/trunk/
76 Adapted pregenerated vhdl files to latest changes ja_rd 4905d 18h /ion/trunk/
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 4905d 18h /ion/trunk/
74 Fixed (harmless) error in simulation template 2 ja_rd 4905d 22h /ion/trunk/
73 Fixed comment about write cycles in cache module ja_rd 4905d 22h /ion/trunk/
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4905d 23h /ion/trunk/
71 Doc updated to reflect last changes ja_rd 4906d 10h /ion/trunk/
70 updated CodeBlocks project file ja_rd 4906d 10h /ion/trunk/

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