OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] - Rev 137

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4795d 11h /ion/trunk/src/
135 Added debug output to synthesizable MPU template. ja_rd 4795d 12h /ion/trunk/src/
131 change to local system-dependent directory path ja_rd 4798d 09h /ion/trunk/src/
130 typo fix ja_rd 4798d 09h /ion/trunk/src/
125 MPU templates now use the real cache by default ja_rd 4798d 10h /ion/trunk/src/
124 Fixed typo in python script header comment ja_rd 4843d 15h /ion/trunk/src/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4843d 18h /ion/trunk/src/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4843d 18h /ion/trunk/src/
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)		 ja_rd 4853d 17h /ion/trunk/src/
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4853d 17h /ion/trunk/src/
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4853d 17h /ion/trunk/src/
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation		 ja_rd 4853d 17h /ion/trunk/src/
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code		 ja_rd 4857d 15h /ion/trunk/src/
106 SW samples updated:
- Added batch files for running the SW simulation		 ja_rd 4857d 16h /ion/trunk/src/
104 FIXED typo in last commit for simulation template ja_rd 4862d 07h /ion/trunk/src/
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4862d 07h /ion/trunk/src/
100 Obsolete synthesizable template files removed ja_rd 4886d 16h /ion/trunk/src/
99 Obsolete TB template files removed ja_rd 4886d 16h /ion/trunk/src/
97 CPU rd and wr data address buses unified ja_rd 4886d 17h /ion/trunk/src/
92 'hello' demo updated to use new startup files ja_rd 4897d 13h /ion/trunk/src/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.