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[/] [ion/] [trunk/] [src/] - Rev 146

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Rev Log message Author Age Path
146 Added D-Cache setup code to 'adventure' bootstrap code
(redundant since common C startup code already does it but...)		 ja_rd 4791d 10h /ion/trunk/src/
144 Added cache setup code to common startup code
Important: the new cache won't work without this		 ja_rd 4791d 10h /ion/trunk/src/
143 'adventure' sample by default will log from 0xb0000000
and simulation length is now longer		 ja_rd 4793d 00h /ion/trunk/src/
142 'Adventure' bootstrap code now enables the cache
(and runs noticeably faster on DE-1 board)		 ja_rd 4793d 00h /ion/trunk/src/
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4793d 18h /ion/trunk/src/
135 Added debug output to synthesizable MPU template. ja_rd 4793d 18h /ion/trunk/src/
131 change to local system-dependent directory path ja_rd 4796d 15h /ion/trunk/src/
130 typo fix ja_rd 4796d 15h /ion/trunk/src/
125 MPU templates now use the real cache by default ja_rd 4796d 16h /ion/trunk/src/
124 Fixed typo in python script header comment ja_rd 4841d 21h /ion/trunk/src/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4842d 00h /ion/trunk/src/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4842d 00h /ion/trunk/src/
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)		 ja_rd 4851d 23h /ion/trunk/src/
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4851d 23h /ion/trunk/src/
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4851d 23h /ion/trunk/src/
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation		 ja_rd 4851d 23h /ion/trunk/src/
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code		 ja_rd 4855d 21h /ion/trunk/src/
106 SW samples updated:
- Added batch files for running the SW simulation		 ja_rd 4855d 22h /ion/trunk/src/
104 FIXED typo in last commit for simulation template ja_rd 4860d 13h /ion/trunk/src/
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4860d 13h /ion/trunk/src/

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