URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] - Rev 36

Rev	Log message	Author	Age	Path
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4914d 09h	/ion/trunk/src/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4914d 09h	/ion/trunk/src/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4916d 08h	/ion/trunk/src/
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4916d 12h	/ion/trunk/src/
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4916d 13h	/ion/trunk/src/
24	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4916d 13h	/ion/trunk/src/
17	dual-ram-block test bench template updated for new mult module	ja_rd	4917d 23h	/ion/trunk/src/
14	Opcode test now has mul/div tests enabled by default	ja_rd	4917d 23h	/ion/trunk/src/
13	single-ram-block test bench template updated for new mult module	ja_rd	4917d 23h	/ion/trunk/src/
9	Trap handling now works as in the MIPS specs: EPC points to victim instruction (break/syscall) Opcode test modified accordingly	ja_rd	4919d 00h	/ion/trunk/src/
4	New test for BREAK: abortion of load and jump Added comment to readme file	ja_rd	4919d 03h	/ion/trunk/src/
2	First commit (includes 'hello' demo)	ja_rd	4919d 13h	/ion/trunk/src/