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Rev Log message Author Age Path
51 Adapted simulation and synth templates for cache module ja_rd 4893d 03h /ion/trunk/src/
50 New code sample: memtest
Tests external RAM		 ja_rd 4893d 03h /ion/trunk/src/
49 'hello' demo: updated to use new cache module
No longer uses temporary hacks or custom linker script		 ja_rd 4893d 03h /ion/trunk/src/
42 Added cache stub module, plus related test bench ja_rd 4897d 06h /ion/trunk/src/
38 Minor changes in header comments ja_rd 4897d 07h /ion/trunk/src/
34 default data address moved to 0x80000000
makefiles and readme files updated accordingly		 ja_rd 4897d 07h /ion/trunk/src/
33 bin2hdl now can initialize 16-bit wide memories ja_rd 4897d 07h /ion/trunk/src/
29 opcode test updated:
supports CP0 cause register and traps in delay slots
tests that traps abort next instruction in all cases		 ja_rd 4899d 05h /ion/trunk/src/
26 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window		 ja_rd 4899d 10h /ion/trunk/src/
25 opcode test:
HO and LO registers tested along with mul/div and not separately		 ja_rd 4899d 10h /ion/trunk/src/
24 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window		 ja_rd 4899d 10h /ion/trunk/src/
17 dual-ram-block test bench template updated for new mult module ja_rd 4900d 20h /ion/trunk/src/
14 Opcode test now has mul/div tests enabled by default ja_rd 4900d 20h /ion/trunk/src/
13 single-ram-block test bench template updated for new mult module ja_rd 4900d 20h /ion/trunk/src/
9 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)
Opcode test modified accordingly		 ja_rd 4901d 22h /ion/trunk/src/
4 New test for BREAK: abortion of load and jump
Added comment to readme file		 ja_rd 4902d 00h /ion/trunk/src/
2 First commit (includes 'hello' demo) ja_rd 4902d 10h /ion/trunk/src/

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