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[/] [ion/] [trunk/] [src/] - Rev 84

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Rev	Log message	Author	Age	Path
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	4891d 16h	/ion/trunk/src/
78	Code sample 'memtest' adapted to test read from flash	ja_rd	4901d 13h	/ion/trunk/src/
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	4901d 13h	/ion/trunk/src/
74	Fixed (harmless) error in simulation template 2	ja_rd	4901d 17h	/ion/trunk/src/
67	Deprecated files: Marked three files as unused, to be removed	ja_rd	4902d 05h	/ion/trunk/src/
66	Code samples: Updated all code samples to use TB2 template and new memory map	ja_rd	4902d 05h	/ion/trunk/src/
65	Fixed io input mux in MPU template 1	ja_rd	4902d 05h	/ion/trunk/src/
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	4903d 19h	/ion/trunk/src/
56	synthesis mpu template updated: BRAM is now one 32-bit-wide block instead of 4 8-bitters (it is read only) python script updated accordingly	ja_rd	4904d 07h	/ion/trunk/src/
55	First version of cache: stub, 1-word cache (forgot to commit new mpu template file)	ja_rd	4904d 08h	/ion/trunk/src/
51	Adapted simulation and synth templates for cache module	ja_rd	4904d 11h	/ion/trunk/src/
50	New code sample: memtest Tests external RAM	ja_rd	4904d 11h	/ion/trunk/src/
49	'hello' demo: updated to use new cache module No longer uses temporary hacks or custom linker script	ja_rd	4904d 11h	/ion/trunk/src/
42	Added cache stub module, plus related test bench	ja_rd	4908d 14h	/ion/trunk/src/
38	Minor changes in header comments	ja_rd	4908d 15h	/ion/trunk/src/
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4908d 15h	/ion/trunk/src/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4908d 15h	/ion/trunk/src/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4910d 13h	/ion/trunk/src/
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4910d 18h	/ion/trunk/src/
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4910d 18h	/ion/trunk/src/

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[/] [ion/] [trunk/] [src/] - Rev 84

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