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[/] [ion/] [trunk/] [src/] [opcodes/] - Rev 198

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Rev	Log message	Author	Age	Path
197	Updated readme stuff for the code samples	ja_rd	4732d 20h	/ion/trunk/src/opcodes/
193	Major test bench reorganization: 1.- TB now uses same object code as synthesizable demo. 2.- TB now simulates full MPU system. 3.- Console logging moved to TB package. 4.- Code sample makefiles and modelsim script updated accordingly.	ja_rd	4732d 21h	/ion/trunk/src/opcodes/
189	fixed opcode test makefile: adapted to new common makefile	ja_rd	4745d 05h	/ion/trunk/src/opcodes/
168	Updated 'opcodes' simulation script to NOT use simulated mips32 instructions and trap instead (as the real CPU does)	ja_rd	4777d 01h	/ion/trunk/src/opcodes/
165	Added (very early draft, very incomplete) reserved opcode trap handler. Updated opcode tester to test some emulated mips32 opcodes using the trap handler.	ja_rd	4782d 11h	/ion/trunk/src/opcodes/
152	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4786d 07h	/ion/trunk/src/opcodes/
150	Bug fix: added missing nop in vacant branch delay slot	ja_rd	4787d 05h	/ion/trunk/src/opcodes/
148	Added optional cache support to 'opcodes' test. Updated simulation length accordingly.	ja_rd	4788d 21h	/ion/trunk/src/opcodes/
110	Updated 'opcodes' code sample: - Longer simulated time for compatibility to new cache	ja_rd	4849d 11h	/ion/trunk/src/opcodes/
106	SW samples updated: - Added batch files for running the SW simulation	ja_rd	4853d 10h	/ion/trunk/src/opcodes/
90	Added 'Adventure' demo to be run from the DE-1 FLASH	ja_rd	4893d 07h	/ion/trunk/src/opcodes/
66	Code samples: Updated all code samples to use TB2 template and new memory map	ja_rd	4903d 21h	/ion/trunk/src/opcodes/
38	Minor changes in header comments	ja_rd	4910d 06h	/ion/trunk/src/opcodes/
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4910d 06h	/ion/trunk/src/opcodes/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4912d 05h	/ion/trunk/src/opcodes/
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4912d 09h	/ion/trunk/src/opcodes/
24	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4912d 10h	/ion/trunk/src/opcodes/
14	Opcode test now has mul/div tests enabled by default	ja_rd	4913d 20h	/ion/trunk/src/opcodes/
9	Trap handling now works as in the MIPS specs: EPC points to victim instruction (break/syscall) Opcode test modified accordingly	ja_rd	4914d 21h	/ion/trunk/src/opcodes/
4	New test for BREAK: abortion of load and jump Added comment to readme file	ja_rd	4915d 00h	/ion/trunk/src/opcodes/

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[/] [ion/] [trunk/] [src/] [opcodes/] - Rev 198

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