OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [tools/] - Rev 101

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically		 ja_rd 4898d 05h /ion/trunk/tools/
70 updated CodeBlocks project file ja_rd 4908d 19h /ion/trunk/tools/
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing		 ja_rd 4908d 19h /ion/trunk/tools/
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.		 ja_rd 4911d 01h /ion/trunk/tools/
44 slite: cleaned up memory allocation/deallocation code ja_rd 4913d 05h /ion/trunk/tools/
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()		 ja_rd 4915d 06h /ion/trunk/tools/
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed		 ja_rd 4915d 06h /ion/trunk/tools/
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 4917d 04h /ion/trunk/tools/
16 SW simulator now shows HI and LO in status ja_rd 4918d 18h /ion/trunk/tools/
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 4919d 06h /ion/trunk/tools/
7 Traps are now simulated as per MIPS specifications:
EPC point to victim instruction (break/syscall)		 ja_rd 4919d 19h /ion/trunk/tools/
5 SW simulator now logs failed assertions instead of quitting ja_rd 4919d 22h /ion/trunk/tools/
2 First commit (includes 'hello' demo) ja_rd 4920d 08h /ion/trunk/tools/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.