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Rev Log message Author Age Path
169 Fixed bug in emulation of CLO instruction
Added support for simulated hardware IRQs (incomplete)		 ja_rd 4792d 20h /ion/trunk/tools/slite/src/
166 Modified simulator, added some debug functionality:
- Optional emulation of some MIPS32r2 opcodes
- Function call trace log using map file (crude implementation)

Plus a few small bug fixes		 ja_rd 4792d 21h /ion/trunk/tools/slite/src/
163 SW simulator update:
Better disassembly format (hastily tested)
New parameters: start address, breakpoint address, whether or not to trap reserved opcodes		 ja_rd 4798d 06h /ion/trunk/tools/slite/src/
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4802d 02h /ion/trunk/tools/slite/src/
147 SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly)		 ja_rd 4804d 15h /ion/trunk/tools/slite/src/
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)		 ja_rd 4865d 05h /ion/trunk/tools/slite/src/
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux		 ja_rd 4869d 04h /ion/trunk/tools/slite/src/
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically		 ja_rd 4909d 01h /ion/trunk/tools/slite/src/
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing		 ja_rd 4919d 15h /ion/trunk/tools/slite/src/
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.		 ja_rd 4921d 21h /ion/trunk/tools/slite/src/
44 slite: cleaned up memory allocation/deallocation code ja_rd 4924d 01h /ion/trunk/tools/slite/src/
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()		 ja_rd 4926d 02h /ion/trunk/tools/slite/src/
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed		 ja_rd 4926d 02h /ion/trunk/tools/slite/src/
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 4928d 00h /ion/trunk/tools/slite/src/
16 SW simulator now shows HI and LO in status ja_rd 4929d 14h /ion/trunk/tools/slite/src/
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 4930d 02h /ion/trunk/tools/slite/src/
7 Traps are now simulated as per MIPS specifications:
EPC point to victim instruction (break/syscall)		 ja_rd 4930d 15h /ion/trunk/tools/slite/src/
5 SW simulator now logs failed assertions instead of quitting ja_rd 4930d 18h /ion/trunk/tools/slite/src/
2 First commit (includes 'hello' demo) ja_rd 4931d 04h /ion/trunk/tools/slite/src/

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